I. 27th of September 1979 Baliga’s paper, “Enhancement

 History Of The IGBT

Whilst working at General Electric in the
1970’s B. Jayant Baliga realised that by combining the most useful aspects of
the metal-oxide-semiconductor (MOS) and the bipolar-junction-transistor (BJT),
high power density could be delivered in a compact form 1. The first step
toward creating such a device had been by a Japanese researcher named Yamagami,
whose 1968 patent was developed over the following decade by others in the
advanced electronics field 2. On the 27th of September 1979
Baliga’s paper, “Enhancement and Depletion Mode Vertical Channel MOS Gated
Thyristors” was published in Electronics Letters which provided experimental
results on fabricated devices, the first IGBTs 1.        

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Physics of Device

A.    Device Structure

An IGBT is a multilayer structure
consisting of: a p+ semiconductor layer at the base known
as the injection layer. This forms a p-n junction in the device which pushes
minority carriers (holes) into the device. A thin sheet of metal is deposited
under this and is used to connect a terminal known as the collector. Above the
p+ layer an n- base layer is placed known as the drift
region; this lightly doped layer controls the forward blocking voltage via its
doping level and width. Two p wells are doped into the base. Finally n+
wells are doped into the p wells and a silicon dioxide (SiO2) layer
on-top of these. A small amount of metal is placed on the SiO2 layer
creating a gate and two emitter contacts. Figure 1 is an illustration of this.
This NPNP structure of this device creates a parasitic thyristor switching this
on creates losses in the device.

Some IGBTs are manufactured with an n+
buffer, layer these are known as punch-through IGBTs (PTIGBT) and those without
as non-punch through (NPTIGBT). The inclusion of a punch-through layer can
significantly improve performance if doping level and thickness of the layer is
carefully selected. Some of the benefits include: low on-state losses at high
blocking voltages, a negative temperature coefficient and removing tail current.
3 Although the benefits of a punch-through IGBT are clear there are some
costs, primarily the n+ layer will reduce the reverse break down
voltage of the device. 

Figure 1. Punch Through IGBT
Structure 3   

B.    Operating Principle

When a gate voltage is applied which is
less than the threshold voltage of the device no inversion layer is formed in
the p type base region, the device is in an “off” state. A very small leakage
current can be detected through the device at this time.

When a gate voltage is applied which is
above the threshold voltage an inversion layer will form in the p type base
region under the cathode, the device is in an “on” state. This inversion layer
creates a conducting channel between the p+ (base) region and the n-
(base) region in this channel, electrons can flow.

The electron current entering the n-
layer causes substantial hole injection from the p+ anode into the n-
base. Although a portion of the holes recombine with the electrons
flowing into the base from the channel, many do not. The majority of the holes,
cross the n- base reaching the p base region where they are then
collected by the metal contacts. 4   

The device can be turned-off by short
circuiting the gate voltage to the cathode which cuts off the supply of electrons
to the base of the p-n-p transistor 3. 

C.    Blocking Voltages

Forward-blocking mode, when a positive
voltage is applied across the collector and emitter terminals the, junctions
between the n+ and p base (j3) and the n+ and
p+ (j1) are forward biased. Conversely the junction
between the p base and n- layers (j2) are reversed
biased. This creates a depletion layer which extends on both sides of the
junction j2 into both the p base and n- region. The
thickness and doping concentration of the n­- base region must be
optimised to achieve the desired blocking voltage.

Reverse-blocking mode, when a negative
voltage is applied across the collector and emitter terminals the junction j1
becomes reverse-biased; the depletion region extends into the n-
base region. The reverse-blocking voltage is determined by an open-base BJT formed
by the p+ layer the n- base and the p base. The desired
reverse voltage capability can be obtained by optimising the resistivity and
thickness of the n- region 5.  


Figure 2. IGBT Structure in
On-State 3    

D.   Conduction Characeristics

Although structurally very similar to a
power MOSFET the operation of an IGBT is much more similar to that of a BJT.
MOSFETs are majority carrier devices but the inclusion of the p+ layer
at the anode is responsible for the minority carrier injection into the n
region, resulting in conductivity modulation 6.

Studying the IGBT equivalent circuit in
figure 2 the voltage drop across the IGBT is the sum of the drop across the p-n
junction and the voltage drop across the driving MOSFET because of this the
on-state voltage drop across the IGBT cannot go below the diode threshold.

The p-n-p transistor here is formed
between the p+ injecting layer (emitter), the n­- type
layer (base) and the p type base (collector). The parasitic n-p-n transistor uses
the n+ buffer (emitter), the p type base (base) and the n-
layer (collector).

Looking at figure 4, the two transistors
connected back-to-back form a parasitic thyristor. The p-n-p transistor switches
on when the collector is at a positive potential with respect to the emitter and
the gate collector current Ic in the IGBT. This collector current
consists of two components Ie, which is the current due to electrons
flowing from the collector to the emitter through the injection layer and Ih,
the hole current flowing from collector to emitter through the p-n-p transistor
and body resistance Rd 7.  

E.    Latching

An interesting phenomenon can be observed
in an IGBT known as latching up. During on-state, holes attracted to the
inversion layer by the negative charge of the electrons travel through the p
base layer and develop a voltage drop in the ohmic resistance of the body. This
voltage will forward bias the n+- p junction and if large enough, a
substantial injection of electrons from the emitter into the p base region will
occur. If this happens the parasitic n-p-n transistor will turn on, with both
the n-p-n and p-n-p transistors turned-on the thyristor that is composed of
this pair will latch up. Once in latch up the gate no longer controls the
collector current (Ic) and the only way to switch off the device is
by forced commutation of the current 8. 


Figure 3. Equivalent Circuit of IGBT 3

Figure 4. Equivalent Circuit of IGBT Showing Current Flow 7




SILVACO Input Files

A.    SILVACO Example File

SILVACO is an extremely powerful tool
that may be used to model a large quantity of semiconductor devices and then
vary any number of their characteristics. Although daunting upon first use
SILVACO offers many example “decks” so that a device can be selected and
modified as the user sees fit. Figure 5 is a sample of the example input file,
which designs the structure of a non-punch through IGBT.

Figure 5. Example Input File

B.    Modifications To Example Deck

The following figures contain changes
made to the example code. The desired effects have been included in the figure

Figure 6. Addition of Gate Voltages to File


Figure 7. Determining Transfer Characteristics


Figure 8. Addition of Gate Voltages to File Continued 


Figure 9. Changes to Doping Concentration 


Figure 10. Changes to Increase Gate Oxide Thickness

Figure 11. Simulating Breakdown Voltage

Results and Discussion

A.    Simulation Structure

The simulation begins by defining the
mesh, materials, electrodes and doping. The materials are given specific
regions in the mesh (refer to figure 5) using the region command before defining the electrode and doping profiles.

transport models for the simulation are
then selected and enabled via the model
command; they reflect the different physical effects that are important to the


Physical Effect


Analytic concentration dependent mobility


Lateral electric field dependent mobility


Surface mobility degradation


Shockley-Read-Hall recombination


Recombination accounting for high level injection effects

Table 1. Models and Their
Physical Effects 9

Figure 12. Structure of
Simulated IGBT

B.    Output Characteristics

Five different gate voltages were
simulated and the results superimposed onto the same graph, these being: 5V,
7V, 9V, 10V and 11V. The IGBT output characteristics were found by declaring
five different gate voltages and increasing the collector voltage from 0 to
20V; the solutions are calculated first with a smaller range before then being
calculated over a larger range, this is to stop convergence errors. Figure 13
shows the results. 

Cut off




Figure 13. Output
Characteristics of IGBT

The graph shows that the device has
several operating regions, these include: the saturation region, the cut off
region and the active region. When the gate voltage is below the threshold
voltage of the device, only a very small leakage current flows, look at the
line VG=5V, the gate voltage was not
large enough for the device to switch on. At this point the collector emitter
voltage is very close to the voltage which is being supplied, the device at
these conditions is operating in the cut off region. The maximum forward
voltage the device could withstand in the cut off region, is determined by the
avalanche breakdown voltage of the p body and n- junction (referred
to earlier as j2) 4.

As the gate voltage increases beyond the
threshold voltage the device enters the active region, here current is flowing
between the emitter and collector terminals, the collector current is
determined by the transfer characteristics of the IGBT.  

The third region of interest is the
saturation region; with the collector bias increasing its electric field starts
to oppose the field created at the gate, reducing the concentration of
electrons in the inversion layer. This leads to a channel “pinch off” enabling
a significant voltage drop across the now depleted channel area. Further
increasing collector bias does not increase the voltage over the junction
injecting the holes (j1) and so collector current Ic no
longer increases also, the device is in the saturation region. Only by
increasing the gate voltage will Ic­ rise 10.     

C.    Transfer Characteristics

The addition of the lines found in figure
7 simulated the transfer characteristics of the IGBT. The solve statements ramp the gate voltage at 0.25V intervals up to a
predefined 10V, the data is saved into a mos1ex01_1
file. The result of this is included in figure 14.



Figure 14. Transfer
Characteristics of IGBT

transfer characteristic is defined as the variation of collector current and
gate bias at a given temperature. The device is in the active region and here
the characteristics are very similar to that of a power MOSFET, reasonably
linear over most of the collector current range.

The ratio of Ic to gate
voltage (Vg) at a given temperature is a measure of the
transconductance (gfs) of the device at that temperature.
Transconductance is an expression of the performance of a transistor; in
general the larger the transconductance of a device, the greater the gain it is
capable of delivering when other factors are held constant.  

                                                                   Equation 1

The calculated transconductance of this
device was 73.148µS. A large gfs is desirable for high current
handling with low gate drive voltage.

Figure 12 shows the devices gate
threshold voltage (Vgth) at 6.0V. As discussed earlier current flow
occurs in the device when an inversion layer forms in the integrated MOSFET
portion of the IGBT. Looking at the equation for Vgth:

 Equation 2

Where Cox is the specific gate
oxide capacitance and NA is the peak doping concentration of the p
base region. Vgth can also be estimated using the following

                           Equation 3

Where tox is the gate oxide
thickness 5. Studying equation 3 it is clear that the threshold voltage will
increase linearly with an increase to the gate oxide thickness and
approximately as the square root of the doping concentration.

D.   Changes To Doping Concentration

Then knowing that a change in doping
concentration in the p body region would affect the transfer characteristics of
the IGBT, the regions doping was increased by 10% from 2.7e17 to 3.0e17.
A comparison of the two results is presented in figure 13.

Gate Bias (V)



Figure 15. Comparison of
Doping Concentrations

The transconductance measured for the
doping value of 3.0e17 was 70.667µS a drop of 3.5%. The reason for
this is that at low voltages a minor concentration of charge carriers are
accelerated. This results in a smaller number of collisions and therefore less
mobility degradation 11.

The threshold voltage of the device did
increase as predicted by equation 3 and it is clearer to see that the earlier
observation of the threshold voltage for the 2.7e17 doping
concentration was incorrect. The Vgth values for the 2.7e17
and 3.0e17 p bodies are 5.1V and 5.3V respectively. The difference
between the two is 3.92% just over the predicted 3.12%. The increase to Vgth
is because when the channel doping concentration increases so does the fermi
potential this leads to a larger depletion layer meaning that the device requires
more effort to deplete the whole channel 11.


Figure 16. Doping
Concentration Increased to 3.2e17

Further increasing the doping
concentration led to a large kink in the transfer characteristics of the IGBT,
illustrated in figure 16. There has been a change in resistance part way
through the device to cause this. The effect may be because the heavy doping of
the p base layer shifts the fermi level, making the device act more like a
metal than a semiconductor and changing the resistivity.

E.    Changes To Oxide Thickness

The gate oxide of the IGBT was also
modified, the oxide layer thickness was increased whilst the p doping
concentration was kept at 2.7e17, the oxide thickness was then
decreased; the two are compared to the IGBT with the original oxide thickness
in figure 17.

Gate Bias (V)


Figure 17. Gate Oxide
Thickness Changes

Studying the results, reducing oxide
thickness decreases threshold voltage (refer to equation 3). Thinning of the
oxide layer increases the capacitance and thus translates to an increase in drive
current capability, meaning an ultra-thin gate oxide needs much lower voltages
to switch on. However decreasing the oxide thickness will result in leakage
current due to the phenomenon of direct tunneling 12. 

By increasing gate oxide thickness Vgth
increases also, as discussed above changing of the oxide layer affects the
capacitance of the junction. By increasing the oxide thickness the capacitance
now decreases, so the device now needs a larger voltage to switch on.

F.     Breakdown Voltage

The maximum voltage that an NPTIGBT can
support is determined by the open-base transistor breakdown. Current generated
via leakage and impact ionization is amplified by the gain of the p-n-p
transistor. Open-base transistor breakdown is given by:

                                   Equation 4

Where YE is the injection
efficiency of the junctions j1 and j2, ?T is
the base transport factor and M is the multiplication factor. The magnitude of ?T
and M is a strong function of the collector bias voltage.